1. Field of the Invention
The present invention relates to a current sensing circuit and a semiconductor memory device including the same, and, more particularly relates to a current-mirror type current sensing circuit and a semiconductor memory device including the same.
2. Description of Related Art
Currently, there are various types of semiconductor memory devices, and DRAM (Dynamic Random Access Memory) can be mentioned as a representative thereof. In DRAMs, information is stored by an amount of charges stored in a cell capacitor. Therefore, in DRAMs, a voltage-sensing type sense amplifier is used.
Meanwhile, in semiconductor memory devices such as flash memory, EEPROM, PRAM (Phase Change Random Access Memory), and RRAM (Resistive Random Access Memory), information is stored by way of an electrical resistance (or conduction/non-conduction) of a memory cell. Thus, as a sense amplifier of this type of semiconductor memory device, a current-sensing type sense amplifier is used (see Japanese Patent Application Laid-open No. 2003-331599).
FIG. 8 is a circuit diagram of a conventional current sensing circuit including a current-sensing type sense amplifier.
A current sensing circuit 10a shown in FIG. 8 is configured by a sense amplifier 20a, a reference cell 30a, and a reference amplifier 40a. The sense amplifier 20a includes a differential amplifier 100 of which one input terminal 100a is connected to a transfer line TRL. The transfer line TRL is connected to a global bit line GBL via a transfer switch TSW, and the global bit line GBL is connected to a bit line BL via a column switch YSW. The bit line BL is connected with a memory cell MC. In an example shown in FIG. 8, the memory cell MC is a PRAM cell composed of a phase-change memory device PC and a selection transistor Tr.
The reference cell 30a has the same circuit configuration as that from the transfer line TRL to the memory cell MC, and generates a reference current Iref. The reference current Iref is supplied to the reference amplifier 40a. The reference amplifier 40a has a P-channel MOS transistor 41 of which the gate and the drain are short-circuited, and accordingly, potentials of the gate and the drain of the transistor 41 are stabled to a level (VREFP) obtained by subtracting a threshold value voltage of the transistor 41 from a power supply potential VDD. The reference potential VREFP is supplied to an input terminal 100b of the differential amplifier 100.
As shown in FIG. 8, the sense amplifier 20a further includes P-channel MOS transistors 21 and 22 connected in series between the power supply potential VDD and the transfer line TRL. A gate of the transistor 21 is supplied with a sense-amplifier activating signal RSAEN, and a gate of the transistor 22 is supplied with the reference potential VREFP.
According to such a configuration, a current mirror circuit is configured in which the transistor 41 is an input transistor and the transistor 22 is an output transistor. Accordingly, when the sense-amplifier activating signal RSAEN is activated, the reference current Iref flows to the transistor 22 (when a current mirror ratio is 1:1).
The sense amplifier 20a includes a precharge transistor 23 that is turned on in response to a precharge signal PRE and a diode-connected transistor 25.
FIG. 9 is a timing chart for explaining an operation of the current sensing circuit 10a. 
As shown in FIG. 9, when a predetermined word line is selected at time t11, a transfer-switch selection signal S, a sense-amplifier activating signal RSAEN, and the precharge signal PRE are activated at subsequent time 12. Thereby, the selected memory cell MC is connected to the transfer line TRL, and also, a potential SAOUT of the input terminal 100a of the differential amplifier 100 reaches a level obtained by subtracting a threshold value voltage of the transistor 25 from the power supply potential VDD. On the other hand, the input terminal 100b of the differential amplifier 100 is directly connected to the current mirror circuit, and thus its potential is VREFP.
The reference potential VREFP supplied to the input terminal 100b is a level obtained by subtracting a threshold value voltage of the transistor 41 from the power supply potential VDD. Thus, when the transistor 25 and the transistor 41 completely match in threshold value, SAOUT and VREFP correctly match in level. However, in reality, there exits a manufacture variation, and thus it is difficult to completely match the threshold values of these transistors. Thus, in reality, SAOUT and VREFP are precharged in an offset state. An example shown in FIG. 9 shows a state that SAOUT is slightly highly precharged as compared to the reference potential VREFP. Needless to mention, there can be an opposite state.
At time 13, the precharge signal PRE is inactivated, and the precharge transistor 23 is turned off. As a result, a precharge operation is completed, and a sense enabled state is established. At this time, by a coupling capacity of the precharge transistor 23, the potential SAOUT of the input terminal 100a is disturbed temporarily and greatly. Such potential fluctuation is one of the causes for offsetting the differential amplifier 100.
Thereafter, the potential SAOUT of the input terminal 100a gradually changes according to a current Icel flowing to the memory cell MC. At time 15, the transfer switch TSW is turned off, and a reading operation from the memory cell MC is ended. At the same time, the sense-amplifier activating signal RSAEN is activated. Thereby, data according to a magnitude relationship between the potential SAOUT and the reference potential VREFP is outputted to a data bus BUS.
However, in the conventional current sensing circuit 10a shown in FIG. 8, SAOUT and VREFP are precharged in an offset state, as described above, and thus it takes a long period of time before an advantageous potential difference occurs between SAOUT and VREF2. It is understood that in the example shown in FIG. 9, even when the memory cell MC is in a set state (a low-resistance state), the levels of SAOUT and VREFP are inverted until time t14. Further, in consideration of the level fluctuation of SAOUT resulting from the coupling capacity of the precharge transistor 23, it is necessary to secure a period T1 (a sensing period) sufficiently long. Thus, there is a problem in the conventional current sensing circuit 10a that the data reading takes time.
Such a problem occurs not only in a current sensing circuit for a PRAM but also in overall current sensing circuits for other semiconductor memory devices such as a current sensing circuit for a flash memory and a current sensing circuit for a RRAM. However, in PRAMs or RRAMs, a cell current is particularly low, and thus the influence exerted by the input offset of the differential amplifier during the data reading time is significantly conspicuous.